As a rule, integrated circuits or chips are already tested at the wafer level, that is to say before being packaged. Such a test is particularly important in the case of semiconductor memories, in particular in the case of dynamic memories or DRAMS (Dynamic Random 15 Access memories), since individual failures of memory cells render the entire memory unusable. As the storage capacity in particular of the dynamic memories increases, the test times greatly increase and have come to give rise to a considerable proportion of the total production costs.
Since the production costs are a significant economic factor in the case of such standard products that are produced in high volumes, great efforts are undertaken to lower said production costs.
One approach consists in reducing the test times of dynamic memories. Another approach consists in testing a plurality of memories in parallel. The capacity of expensive production testers is better utilized as a result of this. Furthermore, the throughput during testing is increased.
A third approach takes a somewhat different direction: a special logic for testing is integrated on a dynamic memory and supports or even completely replaces the external tests. This is already known from the field of logic circuits, where so-called BIST (Built In Self Test) modules which serve for (self-) testing of the microprocessor are integrated for example on complex microprocessors. For this purpose, the BIST modules process test programs for testing individual modules of the processor. Functional test programs are predominantly used. The BIST modules generate the corresponding test patterns.
An external test is thus shorter or can sometimes even be omitted. In particular the number of signals made available by an external tester is thus considerably reduced. Moreover, such a component can also be tested during operation without an external automatic test machine.
For a complete self-test, a test controller or a BIST module must be able to control timings. As a rule, this does not pose any problems for functional tests since the requisite frequencies typically lie in the MHz range. As time base, a chip with such an integrated test controller utilizes an external oscillator clock applied to the chip.
However, this method poses problems in dynamic memories. This is because the latter require in part very slow oscillator clocks for a complete self-test. Such clocks have hitherto been provided by special oscillators which are present in the production testers and which can be programmed independently and asynchronously by the temporal control of the actual test patterns. However, precisely these slow time bases dominate the test time. As a result, a production tester is required for longer. The test throughput is reduced accordingly.
The periodic refresh of the memory cells in functional tests shall be mentioned here as an example of a test sequence of a dynamic memory which requires a particularly slow time base. Further examples are the measurement of the retention time of individual memory cells or the so-called bump test. Each of these tests requires a slow time base in the microseconds or even milliseconds time range.